1. Field of the Invention
This invention relates to a low power logic circuit implementing a logical DOT function and more particularly to a pull-up circuit for complementary field effect transistor logic circuits.
2. Description of the Prior Art
Digital logic circuits such as NOR circuits are well known in the art. Typically, a NOR circuit includes a plurality of signal transistors connected in parallel between an output node and a first fixed potential, each such transistor receiving an independent input signal for turning the transistor on or off. Typically, a load impedance is placed between the output node and a second potential forming a series path between the two potential levels.
In determining the value of resistance of the load impedance, a basic conflict between performance and power dissipation arises. The load impedance should have a very high value for low power dissipation when any of the signal transistors are on. Such a high value of load resistance also helps in keeping the output node as close to the first potential level as possible. With such a high load impedance, however, an excessive amount of time is required to bring the output node to the second potential level after all the signal transistors have been turned off. Moreover, with a high load impedance, the output current available to the output terminal at said second potential level is limited. By lowering the resistance of the load impedance, the current available to the output terminal at said second potential level increases and the transient response of bringing the output node to said second potential is greatly improved. Unfortunately, this improvement goes hand in hand with increasing the power dissipated in the series path between the two potential levels. A further problem arising with the lowered load impedance is that the output node may not be brought completely to the first potential level because of the voltage divider effect between the lower load impedance and the signal transistor.
A well known technical advantage of complementary field effect transistor circuits is that power dissipation is minimized. For this reason alone, the more complex device structure and processing technologies are worth developing. Unfortunately, this very fundamental advantage of CFET circuits is undermined by a load impedance having too low a value of resistance. At the same time, too high a value of load impedance degrades performance beyond acceptable levels. In a simple CFET inverter, consisting of P and N channel FETs connected in series between first and second potential levels, an input signal is simultaneously applied to the gate electrode of both transistors. Thus, the two transistors alternate as load and signal transistors. Such a connection effectively provides a variable load impedance varying from the on and off impedances of the transistors. The output node at the common connection between the two transistors effectively receives a push-pull output dissipating very little power (no DC power) with relatively high performance. Such an arrangement, unfortunately, is not possible if a DOT-OR or DOT-AND connection is desired at the output node.
The foregoing problems with setting the value of load resistors has led to some cumbersome proposed solutions. For example, it has been suggested that the load resistors could be made discrete and off-chip to provide low valued load resistors without exceeding the heat dissipation capacity of the chip. Those skilled in the art will recognize how truly unworkable such a solution would be. Moreover, the problem of excessive power consumption, which is a significant factor in some applications, would still remain. Another proposal would replace the desired DOT-OR function with a complex logic tree to perform the same logic function. This greatly increases the number of devices required on a chip to perform the DOT-OR function.